1. Field of the Invention
The present invention relates to techniques for improving circuit performance. More specifically, the present invention relates to a method for performing a constrained optimization to determine circuit parameters.
2. Related Art
The circuit in FIG. 1 illustrates the series of challenges facing the modern integrated circuit designer. Note that the circuit includes a path of N+1 gates with side loads. For the purposes of illustration, assume that a gate i has a drive strength xi. In addition, assume that both the drive strength (x0) of gate 0 and the side loads are fixed.
The first challenge is finding the drive strengths xi, 0<i≦N, that minimize the transistor area A of this path under the constraint that the total path delay is at most D0. A more general question is to find the minimal transistor area A(D0) as a function of the delay constraint D0. This “cost function” reveals to the designer how the cost in terms of transistor area behaves as a function of the delay constraint D0. Knowing this cost function permits a designer to choose the best trade-off between area and path delay.
The inverse of the first challenge is to find the drive strengths xi, 0<i≦N, that minimize the path delay D of this path under the constraint that the total transistor area of the path is at most A0. Here, the more general question is to find the minimal path delay D(A0) as a function of the area constraint A0. This cost function reveals to the designer how the cost in terms of minimum path delay behaves as a function of the area constraint A0.
A different, but similar, challenge is to find the drive strengths xi, 0<i≦N, that minimize the energy dissipation E of the path under the constraint that the total path delay is at most D0. For this problem, we want to find how the cost E(D0) in terms of energy behaves as a function of the delay constraint D0. Conversely, we also want to find how the minimum path delay D(E0) behaves as a function of the energy constraint E0.
Another challenge arises with a cyclic path. In the case of a cyclic path, the path delay becomes the cycle time and the function A(D0) represents the transistor area for a constraint D0 on the cycle time. Conversely, D(A0) represents the minimum cycle time for the constraint A0 on the transistor area.
Researchers have proposed multiple solutions to the above-described constrained circuit optimization problems. Unfortunately, the proposed solutions fall short in one aspect or another, thereby limiting their effectiveness for many applications of interest. For example, several of the proposed solutions employ over-inclusive or non-convergent modeling techniques, which lead to prohibitive run-times or outright failure in some applications.
Hence, what is needed is a method for performing a constrained optimization to determine circuit parameters in a manner which expediently and accurately converges on a useful solution.